Design of open DEEC based on TTP/C bus and verification of PIL simulation
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摘要: 基于自主设计的TTP/C(时间触发协议)总线控制器,提出了开放式DEEC(发动机数字式电子控制器)的冗余架构,将其划分为输入、核心计算及输出3种智能节点,并制定了各个智能节点的任务调度规划图.设计了基于DSP(digital signal processor)+FPGA(field-programmable gate array)的智能节点硬件平台,在此基础上完成各智能节点的软件设计.最后构建了开放式DEEC的PIL(process in the loop)仿真测试平台,以发动机模型为控制对象,展开了状态调节试验和总线故障注入试验.试验结果证明该开放式DEEC是可行的,并具有良好的重构特性.
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关键词:
- 发动机数字式电子控制器 /
- TTP/C总线 /
- 开放式架构 /
- PIL仿真 /
- 重构
Abstract: With the self-development TTP/C (time trigger protocol/automotive class C) bus controller, a redundant architecture of open DEEC (digital electronic engine controller) was proposed, which was divided into three kinds of intelligent nodes: input, core calculation and output, and the task scheduling for each intelligent node was planned. Hardware platform of intelligent node was designed based on DSP (digital signal processor) and FPGA (field-programmable gate array), and the software was designed for each intelligent node. Finally, a PIL (process in the loop) simulation test platform for open DEEC was constructed.With an engine model as the controlled object, the state regulation experiments and bus fault injection experiments were conducted.The experiment results show that the open DEEC architecture is feasible and has a good reconstruction ability.-
Key words:
- DEEC /
- TTP/C bus /
- open architecture /
- PIL simulation /
- reconstruction
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