面向电子控制器测试的JTAG控制器IP软核设计

杨聖魁; 张天宏; 邓志伟

面向电子控制器测试的JTAG控制器IP软核设计

1.
南京航空航天大学能源与动力学院,南京 210016
2.
中国航空工业集团公司中国航空动力控制系统研究所,无锡 214063

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出版历程
- 收稿日期: 2009-11-30
- 修回日期: 2010-08-31
- 刊出日期: 2011-01-28

Design of the IP soft core of JTAG controller for electronic engine controller

1.
College of Energy and Power Engineering, Nanjing University of Aeronautics and Astronautics,Nanjing 210016,China
2.
Aviation Motor Control System Institute, Aviation Industry Corporation of China,Wuxi 214063,China

摘要

摘要: 基于可编程门阵列(FPGA)设计JTAG (joint test action group)控制器知识产权(IP)软核,可以实现在线测试.通过分析测试访问端口(TAP)控制器状态机及边界扫描专用控制器芯片原理,针对发动机控制器中常用的数字信号处理器(DSP)芯片,设计了JTAG控制器IP软核以及基于该IP软核的边界扫描测试验证系统的硬件电路,完成了主要指令的测试.采用该IP软核可以灵活地加载扫描矢量,实现在线测试.该设计可以用于扫描测试、故障注入等多个领域.
- 发动机电子控制器 /
- 边界扫描 /
- 机内测试 /
- 可编程门阵列 /
- 知识产权软核
Abstract: It is feasible to realize on-line test by designing an intellectual property (IP) soft core of JTAG (joint test action group) controller which is based on filed-programmable gate array (FPGA).Through analyzing the state machine of test access port (TAP) controller and the principle of some application specific integrated circuit (ASIC) for boundary scan controller,the IP soft core of JTAG controller was designed for digital signal process (DSP) which was used in an electronic engine controller (EEC).Meanwhile the hardware of testing and verification system for boundary scan was designed,and the tests of main instructions were completed.This IP soft core,which can be used in many fields such as scan test and fault injection,can load the scan vector flexibly to realize on-line test.
- electronic engine controller(EEC) /
- boundary scan /
- built in test(BIT) /
- field-programmable gate array(FPGA) /
- intellectual property (IP) soft core

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参考文献(13)

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